1. Field of the Invention
The present invention relates to a test key structure, and more particularly, to a test key for monitoring gate conductor-deep trench (GC-DT) misalignment in the fabrication of deep-trench dynamic random access memories (DRAMs).
2. Description of the Prior Art
In semiconductor fabrication, a semiconductor device or an integrated circuit (IC) is continuously tested in every step so as to maintain the quality of the IC. Ordinarily, a testing circuit is simultaneously fabricated with an actual device so that the quality of the actual device can be assessed by the performance of the testing circuit. The quality of the actual device therefore can be well controlled. Typically, such testing circuit, which is also referred to as “test key”, is disposed on a peripheral area of each chip or die.
A typical method to test a wafer is called a wafer acceptance testing (WAT) method, which can measure defects of the wafer. The WAT method includes providing several test keys distributed in the periphery region of a die. The test keys typically are formed on a scribe line between dies, and are electrically coupled to an external terminal through a metal pad. A module of the test keys is selected and each test key off the selected module is respectively used for a test of different property of the wafer, such as threshold voltage (VTH) or saturate current IDSAT. A controlled bias is applied to the test keys, and the induced current is read out to detect defects on the wafer.
As known in the art, in trench DRAM fabrication, the process window for gate conductor-deep trench (GC-DT) misalignment is small. There is a strong need to provide an effective test key structure for monitoring the GC-DT misalignment during the fabrication of trench capacitor DRAMs, especially for the DRAM process using 90 nm line width standard.